The subject matter disclosed herein is concerned with liquid crystal display (LCD) devices, which in particular relates to source drivers employed in LCD devices.
LCD devices are widely used in notebook computers, LCD televisions, mobile phones, and so forth on their merits of miniaturization and low power consumption. Especially, LCD devices of active matrix type, utilizing thin-film transistors (TFT) as switching elements, are highly adaptable to displaying motion pictures.
FIG. 1 is a schematic diagram showing a conventional, general LCD device. Referring to FIG. 1, the LCD device has an LCD panel 3000, a source driver block 1000 including pluralities of source drivers connected to pluralities of source lines SL, and a gate driver block 2000 including pluralities of gate drivers GD connected to pluralities of gate lines GL. The source line is also referred to as data line or channel.
Source drivers (SD) 100 of the source driver block 1000 activate the source lines SL arranged on the LCD panel 3000, respectively. Gate drivers (GD) 200 of the gate driver block 2000 activate the gate lines GL arranged on the LCD panel 3000, respectively.
The LCD panel 3000 includes pluralities of pixels 300. Each pixel is composed of a switching transistor TR, a storage capacitor CST reducing current leakage from the pixel, and a liquid crystal capacitor CLC. The switching transistor TR is turned on or off in response to a signal driving the gate line GL. The switching transistor TR is connected to the source line SL through the drain terminal thereof. The storage capacitor CST is coupled between the source terminal of the switching transistor TR and a ground voltage terminal VSS. The liquid crystal capacitor CLC is coupled between the source terminal of the switching transistor TR and a common voltage terminal VCOM. For example, the common voltage VCOM may be half of a power source voltage, i.e., VDD/2.
FIG. 2 is a circuit diagram of the conventional source driver 100 shown in FIG. 1. Referring to FIG. 2, the source driver 100 includes a digital-to-analogue converter (DAC) 110, output buffers 120, output switches 130, and charge-sharing switches 140.
The DAC 110 transforms digital image signals into analogue image signals. The analogue image signals from the DAC 110 represent gray-level voltages.
The output buffers 120 amplify the analogue image signals and transfer the amplified signals to the output switches 130, respectively. The output switches 130 generate source-line driving signals Y1˜Yn from the amplified analogue image signals, respectively, in response to output-switch control signals OSW and /OSW. The source-line driving signals Y1˜Yn are applied to loads (LD) 150 that are connected to the source lines.
FIG. 3 is a circuit diagram of the conventional output buffer 120 shown FIG. 2. Referring to FIG. 3, the output buffer 120 is a rail-to-rail operation amplifier. The output buffer 120 includes an input circuit 121, an amplifier circuit 122, a capacitive circuit 123, and an output circuit 124, in the configuration of voltage follower where an output signal OUT is inverted and fed back as input signals INP and INN through a feedback loop. The first input signal INP is the analogue image signal and the second input signal INN is the source-line driving signal.
A slew rate of the output voltage from the convention output buffer 120 is given by the following equation.
                    SR        ≡                              ⅆ            Vout                                ⅆ            t                          ≡                              (                                          IMP                ⁢                                                                  ⁢                3                            +                              IMN                ⁢                                                                  ⁢                3                                      )                                2            ⁢            C                                              (        1        )            
In Equation 1, Vout is the output voltage of the output buffer 120. IMP3 denotes the amount of current flowing through a third PMOS transistor MP3, and IMN3 denotes the amount of current flowing through a third NMOS transistor MN3. C represents capacitance of a capacitor of the capacitive circuit 123.
FIG. 4 is a timing diagram for the conventional output buffer 120 showing distortion in the common voltage caused by an increased slew rate of a source-line driving signal. When a slew rate of the source-line driving signal (e.g., Y1 of FIG. 2) becomes higher, the source-line driving signal Y1 abruptly increases or decreases. Thus, it results in distortion of the common voltage VCOM that is being coupled to the source-line driving signal Y1 and the source line SL. From the distortion of the common voltage VCOM, there occurs the phenomenon of noises on the display panel or image blinking.